`timescale 1ns/1ns
module jk_trigger_tb;
reg j,k,clk,rst=1;
wire q;

jk_trigger u1(.j(j), .k(k), .clk(clk), .q(q), .rst(rst));
initial begin
	clk = 0;
	rst = 0;
	j = 1'b0;
	k = 1'b0;
	#30 j = 1'b0; k = 1'b1;
	#20 j = 1'b1; k = 1'b0;
	#20 j = 1'b1; k = 1'b1;
	#20 j = 1'b1; k = 1'b0;
	#20 j = 1'b0; k = 1'b0;
end

always begin
	#10 clk = ~clk;
end

endmodule
